// name:array_19_ext depth:1024 width:7 masked:false maskGran:7 maskSeg:1
module array_19_ext(
  input RW0_clk,
  input [9:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [6:0] RW0_wdata,
  output [6:0] RW0_rdata
);


  reg reg_RW0_ren;
  reg [9:0] reg_RW0_addr;
  reg [6:0] ram [1023:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 1024; initvar = initvar+1)
        ram[initvar] = {1 {$random}};
      reg_RW0_addr = {1 {$random}};
    end
  `endif
  always @(posedge RW0_clk)
    reg_RW0_ren <= RW0_en && !RW0_wmode;
  always @(posedge RW0_clk)
    if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
  always @(posedge RW0_clk)
    if (RW0_en && RW0_wmode) begin
      ram[RW0_addr][6:0] <= RW0_wdata[6:0];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [31:0] RW0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      RW0_random = {$random};
      reg_RW0_ren = RW0_random[0];
    end
  `endif
  always @(posedge RW0_clk) RW0_random <= {$random};
  assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[6:0];
  `else
  assign RW0_rdata = ram[reg_RW0_addr];
  `endif

endmodule// name:array_18_ext depth:1024 width:160 masked:true maskGran:20 maskSeg:8
module array_18_ext(
  input RW0_clk,
  input [9:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [7:0] RW0_wmask,
  input [159:0] RW0_wdata,
  output [159:0] RW0_rdata
);


  reg reg_RW0_ren;
  reg [9:0] reg_RW0_addr;
  reg [159:0] ram [1023:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 1024; initvar = initvar+1)
        ram[initvar] = {5 {$random}};
      reg_RW0_addr = {1 {$random}};
    end
  `endif
  always @(posedge RW0_clk)
    reg_RW0_ren <= RW0_en && !RW0_wmode;
  always @(posedge RW0_clk)
    if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
  always @(posedge RW0_clk)
    if (RW0_en && RW0_wmode) begin
      if (RW0_wmask[0]) ram[RW0_addr][19:0] <= RW0_wdata[19:0];
      if (RW0_wmask[1]) ram[RW0_addr][39:20] <= RW0_wdata[39:20];
      if (RW0_wmask[2]) ram[RW0_addr][59:40] <= RW0_wdata[59:40];
      if (RW0_wmask[3]) ram[RW0_addr][79:60] <= RW0_wdata[79:60];
      if (RW0_wmask[4]) ram[RW0_addr][99:80] <= RW0_wdata[99:80];
      if (RW0_wmask[5]) ram[RW0_addr][119:100] <= RW0_wdata[119:100];
      if (RW0_wmask[6]) ram[RW0_addr][139:120] <= RW0_wdata[139:120];
      if (RW0_wmask[7]) ram[RW0_addr][159:140] <= RW0_wdata[159:140];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [159:0] RW0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      RW0_random = {$random, $random, $random, $random, $random};
      reg_RW0_ren = RW0_random[0];
    end
  `endif
  always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random};
  assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[159:0];
  `else
  assign RW0_rdata = ram[reg_RW0_addr];
  `endif

endmodule// name:array_17_ext depth:1024 width:56 masked:true maskGran:7 maskSeg:8
module array_17_ext(
  input RW0_clk,
  input [9:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [7:0] RW0_wmask,
  input [55:0] RW0_wdata,
  output [55:0] RW0_rdata
);


  reg reg_RW0_ren;
  reg [9:0] reg_RW0_addr;
  reg [55:0] ram [1023:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 1024; initvar = initvar+1)
        ram[initvar] = {2 {$random}};
      reg_RW0_addr = {1 {$random}};
    end
  `endif
  always @(posedge RW0_clk)
    reg_RW0_ren <= RW0_en && !RW0_wmode;
  always @(posedge RW0_clk)
    if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
  always @(posedge RW0_clk)
    if (RW0_en && RW0_wmode) begin
      if (RW0_wmask[0]) ram[RW0_addr][6:0] <= RW0_wdata[6:0];
      if (RW0_wmask[1]) ram[RW0_addr][13:7] <= RW0_wdata[13:7];
      if (RW0_wmask[2]) ram[RW0_addr][20:14] <= RW0_wdata[20:14];
      if (RW0_wmask[3]) ram[RW0_addr][27:21] <= RW0_wdata[27:21];
      if (RW0_wmask[4]) ram[RW0_addr][34:28] <= RW0_wdata[34:28];
      if (RW0_wmask[5]) ram[RW0_addr][41:35] <= RW0_wdata[41:35];
      if (RW0_wmask[6]) ram[RW0_addr][48:42] <= RW0_wdata[48:42];
      if (RW0_wmask[7]) ram[RW0_addr][55:49] <= RW0_wdata[55:49];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [63:0] RW0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      RW0_random = {$random, $random};
      reg_RW0_ren = RW0_random[0];
    end
  `endif
  always @(posedge RW0_clk) RW0_random <= {$random, $random};
  assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[55:0];
  `else
  assign RW0_rdata = ram[reg_RW0_addr];
  `endif

endmodule// name:array_16_ext depth:128 width:230 masked:true maskGran:23 maskSeg:10
module array_16_ext(
  input RW0_clk,
  input [6:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [9:0] RW0_wmask,
  input [229:0] RW0_wdata,
  output [229:0] RW0_rdata
);


  reg reg_RW0_ren;
  reg [6:0] reg_RW0_addr;
  reg [229:0] ram [127:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 128; initvar = initvar+1)
        ram[initvar] = {8 {$random}};
      reg_RW0_addr = {1 {$random}};
    end
  `endif
  always @(posedge RW0_clk)
    reg_RW0_ren <= RW0_en && !RW0_wmode;
  always @(posedge RW0_clk)
    if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
  always @(posedge RW0_clk)
    if (RW0_en && RW0_wmode) begin
      if (RW0_wmask[0]) ram[RW0_addr][22:0] <= RW0_wdata[22:0];
      if (RW0_wmask[1]) ram[RW0_addr][45:23] <= RW0_wdata[45:23];
      if (RW0_wmask[2]) ram[RW0_addr][68:46] <= RW0_wdata[68:46];
      if (RW0_wmask[3]) ram[RW0_addr][91:69] <= RW0_wdata[91:69];
      if (RW0_wmask[4]) ram[RW0_addr][114:92] <= RW0_wdata[114:92];
      if (RW0_wmask[5]) ram[RW0_addr][137:115] <= RW0_wdata[137:115];
      if (RW0_wmask[6]) ram[RW0_addr][160:138] <= RW0_wdata[160:138];
      if (RW0_wmask[7]) ram[RW0_addr][183:161] <= RW0_wdata[183:161];
      if (RW0_wmask[8]) ram[RW0_addr][206:184] <= RW0_wdata[206:184];
      if (RW0_wmask[9]) ram[RW0_addr][229:207] <= RW0_wdata[229:207];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [255:0] RW0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random};
      reg_RW0_ren = RW0_random[0];
    end
  `endif
  always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random};
  assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[229:0];
  `else
  assign RW0_rdata = ram[reg_RW0_addr];
  `endif

endmodule// name:array_15_ext depth:128 width:40 masked:true maskGran:4 maskSeg:10
module array_15_ext(
  input RW0_clk,
  input [6:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [9:0] RW0_wmask,
  input [39:0] RW0_wdata,
  output [39:0] RW0_rdata
);


  reg reg_RW0_ren;
  reg [6:0] reg_RW0_addr;
  reg [39:0] ram [127:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 128; initvar = initvar+1)
        ram[initvar] = {2 {$random}};
      reg_RW0_addr = {1 {$random}};
    end
  `endif
  always @(posedge RW0_clk)
    reg_RW0_ren <= RW0_en && !RW0_wmode;
  always @(posedge RW0_clk)
    if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
  always @(posedge RW0_clk)
    if (RW0_en && RW0_wmode) begin
      if (RW0_wmask[0]) ram[RW0_addr][3:0] <= RW0_wdata[3:0];
      if (RW0_wmask[1]) ram[RW0_addr][7:4] <= RW0_wdata[7:4];
      if (RW0_wmask[2]) ram[RW0_addr][11:8] <= RW0_wdata[11:8];
      if (RW0_wmask[3]) ram[RW0_addr][15:12] <= RW0_wdata[15:12];
      if (RW0_wmask[4]) ram[RW0_addr][19:16] <= RW0_wdata[19:16];
      if (RW0_wmask[5]) ram[RW0_addr][23:20] <= RW0_wdata[23:20];
      if (RW0_wmask[6]) ram[RW0_addr][27:24] <= RW0_wdata[27:24];
      if (RW0_wmask[7]) ram[RW0_addr][31:28] <= RW0_wdata[31:28];
      if (RW0_wmask[8]) ram[RW0_addr][35:32] <= RW0_wdata[35:32];
      if (RW0_wmask[9]) ram[RW0_addr][39:36] <= RW0_wdata[39:36];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [63:0] RW0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      RW0_random = {$random, $random};
      reg_RW0_ren = RW0_random[0];
    end
  `endif
  always @(posedge RW0_clk) RW0_random <= {$random, $random};
  assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[39:0];
  `else
  assign RW0_rdata = ram[reg_RW0_addr];
  `endif

endmodule// name:array_14_ext depth:8192 width:64 masked:false maskGran:64 maskSeg:1
module array_14_ext(
  input RW0_clk,
  input [12:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [63:0] RW0_wdata,
  output [63:0] RW0_rdata
);


  reg reg_RW0_ren;
  reg [12:0] reg_RW0_addr;
  reg [63:0] ram [8191:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 8192; initvar = initvar+1)
        ram[initvar] = {2 {$random}};
      reg_RW0_addr = {1 {$random}};
    end
  `endif
  always @(posedge RW0_clk)
    reg_RW0_ren <= RW0_en && !RW0_wmode;
  always @(posedge RW0_clk)
    if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
  always @(posedge RW0_clk)
    if (RW0_en && RW0_wmode) begin
      ram[RW0_addr][63:0] <= RW0_wdata[63:0];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [63:0] RW0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      RW0_random = {$random, $random};
      reg_RW0_ren = RW0_random[0];
    end
  `endif
  always @(posedge RW0_clk) RW0_random <= {$random, $random};
  assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[63:0];
  `else
  assign RW0_rdata = ram[reg_RW0_addr];
  `endif

endmodule// name:array_13_ext depth:64 width:192 masked:true maskGran:24 maskSeg:8
module array_13_ext(
  input RW0_clk,
  input [5:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [7:0] RW0_wmask,
  input [191:0] RW0_wdata,
  output [191:0] RW0_rdata
);


  reg reg_RW0_ren;
  reg [5:0] reg_RW0_addr;
  reg [191:0] ram [63:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 64; initvar = initvar+1)
        ram[initvar] = {6 {$random}};
      reg_RW0_addr = {1 {$random}};
    end
  `endif
  always @(posedge RW0_clk)
    reg_RW0_ren <= RW0_en && !RW0_wmode;
  always @(posedge RW0_clk)
    if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
  always @(posedge RW0_clk)
    if (RW0_en && RW0_wmode) begin
      if (RW0_wmask[0]) ram[RW0_addr][23:0] <= RW0_wdata[23:0];
      if (RW0_wmask[1]) ram[RW0_addr][47:24] <= RW0_wdata[47:24];
      if (RW0_wmask[2]) ram[RW0_addr][71:48] <= RW0_wdata[71:48];
      if (RW0_wmask[3]) ram[RW0_addr][95:72] <= RW0_wdata[95:72];
      if (RW0_wmask[4]) ram[RW0_addr][119:96] <= RW0_wdata[119:96];
      if (RW0_wmask[5]) ram[RW0_addr][143:120] <= RW0_wdata[143:120];
      if (RW0_wmask[6]) ram[RW0_addr][167:144] <= RW0_wdata[167:144];
      if (RW0_wmask[7]) ram[RW0_addr][191:168] <= RW0_wdata[191:168];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [191:0] RW0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      RW0_random = {$random, $random, $random, $random, $random, $random};
      reg_RW0_ren = RW0_random[0];
    end
  `endif
  always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random};
  assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[191:0];
  `else
  assign RW0_rdata = ram[reg_RW0_addr];
  `endif

endmodule// name:array_12_ext depth:64 width:64 masked:false maskGran:64 maskSeg:1
module array_12_ext(
  input RW0_clk,
  input [5:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [63:0] RW0_wdata,
  output [63:0] RW0_rdata
);


  reg reg_RW0_ren;
  reg [5:0] reg_RW0_addr;
  reg [63:0] ram [63:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 64; initvar = initvar+1)
        ram[initvar] = {2 {$random}};
      reg_RW0_addr = {1 {$random}};
    end
  `endif
  always @(posedge RW0_clk)
    reg_RW0_ren <= RW0_en && !RW0_wmode;
  always @(posedge RW0_clk)
    if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
  always @(posedge RW0_clk)
    if (RW0_en && RW0_wmode) begin
      ram[RW0_addr][63:0] <= RW0_wdata[63:0];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [63:0] RW0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      RW0_random = {$random, $random};
      reg_RW0_ren = RW0_random[0];
    end
  `endif
  always @(posedge RW0_clk) RW0_random <= {$random, $random};
  assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[63:0];
  `else
  assign RW0_rdata = ram[reg_RW0_addr];
  `endif

endmodule// name:array_11_ext depth:4 width:2672 masked:true maskGran:334 maskSeg:8
module array_11_ext(
  input RW0_clk,
  input [1:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [7:0] RW0_wmask,
  input [2671:0] RW0_wdata,
  output [2671:0] RW0_rdata
);


  reg reg_RW0_ren;
  reg [1:0] reg_RW0_addr;
  reg [2671:0] ram [3:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 4; initvar = initvar+1)
        ram[initvar] = {84 {$random}};
      reg_RW0_addr = {1 {$random}};
    end
  `endif
  always @(posedge RW0_clk)
    reg_RW0_ren <= RW0_en && !RW0_wmode;
  always @(posedge RW0_clk)
    if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
  always @(posedge RW0_clk)
    if (RW0_en && RW0_wmode) begin
      if (RW0_wmask[0]) ram[RW0_addr][333:0] <= RW0_wdata[333:0];
      if (RW0_wmask[1]) ram[RW0_addr][667:334] <= RW0_wdata[667:334];
      if (RW0_wmask[2]) ram[RW0_addr][1001:668] <= RW0_wdata[1001:668];
      if (RW0_wmask[3]) ram[RW0_addr][1335:1002] <= RW0_wdata[1335:1002];
      if (RW0_wmask[4]) ram[RW0_addr][1669:1336] <= RW0_wdata[1669:1336];
      if (RW0_wmask[5]) ram[RW0_addr][2003:1670] <= RW0_wdata[2003:1670];
      if (RW0_wmask[6]) ram[RW0_addr][2337:2004] <= RW0_wdata[2337:2004];
      if (RW0_wmask[7]) ram[RW0_addr][2671:2338] <= RW0_wdata[2671:2338];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [2687:0] RW0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
      reg_RW0_ren = RW0_random[0];
    end
  `endif
  always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
  assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[2671:0];
  `else
  assign RW0_rdata = ram[reg_RW0_addr];
  `endif

endmodule// name:array_10_ext depth:4 width:1044 masked:true maskGran:261 maskSeg:4
module array_10_ext(
  input RW0_clk,
  input [1:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [3:0] RW0_wmask,
  input [1043:0] RW0_wdata,
  output [1043:0] RW0_rdata
);


  reg reg_RW0_ren;
  reg [1:0] reg_RW0_addr;
  reg [1043:0] ram [3:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 4; initvar = initvar+1)
        ram[initvar] = {33 {$random}};
      reg_RW0_addr = {1 {$random}};
    end
  `endif
  always @(posedge RW0_clk)
    reg_RW0_ren <= RW0_en && !RW0_wmode;
  always @(posedge RW0_clk)
    if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
  always @(posedge RW0_clk)
    if (RW0_en && RW0_wmode) begin
      if (RW0_wmask[0]) ram[RW0_addr][260:0] <= RW0_wdata[260:0];
      if (RW0_wmask[1]) ram[RW0_addr][521:261] <= RW0_wdata[521:261];
      if (RW0_wmask[2]) ram[RW0_addr][782:522] <= RW0_wdata[782:522];
      if (RW0_wmask[3]) ram[RW0_addr][1043:783] <= RW0_wdata[1043:783];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [1055:0] RW0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
      reg_RW0_ren = RW0_random[0];
    end
  `endif
  always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
  assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[1043:0];
  `else
  assign RW0_rdata = ram[reg_RW0_addr];
  `endif

endmodule// name:array_9_ext depth:8 width:256 masked:false maskGran:256 maskSeg:1
module array_9_ext(
  input R0_clk,
  input [2:0] R0_addr,
  input R0_en,
  output [255:0] R0_data,
  input W0_clk,
  input [2:0] W0_addr,
  input W0_en,
  input [255:0] W0_data
);


  reg reg_R0_ren;
  reg [2:0] reg_R0_addr;
  reg [255:0] ram [7:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 8; initvar = initvar+1)
        ram[initvar] = {8 {$random}};
      reg_R0_addr = {1 {$random}};
    end
  `endif
  always @(posedge R0_clk)
    reg_R0_ren <= R0_en;
  always @(posedge R0_clk)
    if (R0_en) reg_R0_addr <= R0_addr;
  always @(posedge W0_clk)
    if (W0_en) begin
      ram[W0_addr][255:0] <= W0_data[255:0];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [255:0] R0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      R0_random = {$random, $random, $random, $random, $random, $random, $random, $random};
      reg_R0_ren = R0_random[0];
    end
  `endif
  always @(posedge R0_clk) R0_random <= {$random, $random, $random, $random, $random, $random, $random, $random};
  assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[255:0];
  `else
  assign R0_data = ram[reg_R0_addr];
  `endif

endmodule// name:array_8_ext depth:8 width:236 masked:false maskGran:236 maskSeg:1
module array_8_ext(
  input R0_clk,
  input [2:0] R0_addr,
  input R0_en,
  output [235:0] R0_data,
  input W0_clk,
  input [2:0] W0_addr,
  input W0_en,
  input [235:0] W0_data
);


  reg reg_R0_ren;
  reg [2:0] reg_R0_addr;
  reg [235:0] ram [7:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 8; initvar = initvar+1)
        ram[initvar] = {8 {$random}};
      reg_R0_addr = {1 {$random}};
    end
  `endif
  always @(posedge R0_clk)
    reg_R0_ren <= R0_en;
  always @(posedge R0_clk)
    if (R0_en) reg_R0_addr <= R0_addr;
  always @(posedge W0_clk)
    if (W0_en) begin
      ram[W0_addr][235:0] <= W0_data[235:0];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [255:0] R0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      R0_random = {$random, $random, $random, $random, $random, $random, $random, $random};
      reg_R0_ren = R0_random[0];
    end
  `endif
  always @(posedge R0_clk) R0_random <= {$random, $random, $random, $random, $random, $random, $random, $random};
  assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[235:0];
  `else
  assign R0_data = ram[reg_R0_addr];
  `endif

endmodule// name:array_7_ext depth:128 width:100 masked:true maskGran:50 maskSeg:2
module array_7_ext(
  input RW0_clk,
  input [6:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [1:0] RW0_wmask,
  input [99:0] RW0_wdata,
  output [99:0] RW0_rdata
);


  reg reg_RW0_ren;
  reg [6:0] reg_RW0_addr;
  reg [99:0] ram [127:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 128; initvar = initvar+1)
        ram[initvar] = {4 {$random}};
      reg_RW0_addr = {1 {$random}};
    end
  `endif
  always @(posedge RW0_clk)
    reg_RW0_ren <= RW0_en && !RW0_wmode;
  always @(posedge RW0_clk)
    if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
  always @(posedge RW0_clk)
    if (RW0_en && RW0_wmode) begin
      if (RW0_wmask[0]) ram[RW0_addr][49:0] <= RW0_wdata[49:0];
      if (RW0_wmask[1]) ram[RW0_addr][99:50] <= RW0_wdata[99:50];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [127:0] RW0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      RW0_random = {$random, $random, $random, $random};
      reg_RW0_ren = RW0_random[0];
    end
  `endif
  always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random};
  assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[99:0];
  `else
  assign RW0_rdata = ram[reg_RW0_addr];
  `endif

endmodule// name:array_6_ext depth:128 width:50 masked:false maskGran:50 maskSeg:1
module array_6_ext(
  input RW0_clk,
  input [6:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [49:0] RW0_wdata,
  output [49:0] RW0_rdata
);


  reg reg_RW0_ren;
  reg [6:0] reg_RW0_addr;
  reg [49:0] ram [127:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 128; initvar = initvar+1)
        ram[initvar] = {2 {$random}};
      reg_RW0_addr = {1 {$random}};
    end
  `endif
  always @(posedge RW0_clk)
    reg_RW0_ren <= RW0_en && !RW0_wmode;
  always @(posedge RW0_clk)
    if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
  always @(posedge RW0_clk)
    if (RW0_en && RW0_wmode) begin
      ram[RW0_addr][49:0] <= RW0_wdata[49:0];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [63:0] RW0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      RW0_random = {$random, $random};
      reg_RW0_ren = RW0_random[0];
    end
  `endif
  always @(posedge RW0_clk) RW0_random <= {$random, $random};
  assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[49:0];
  `else
  assign RW0_rdata = ram[reg_RW0_addr];
  `endif

endmodule// name:array_5_ext depth:256 width:24 masked:true maskGran:6 maskSeg:4
module array_5_ext(
  input R0_clk,
  input [7:0] R0_addr,
  input R0_en,
  output [23:0] R0_data,
  input W0_clk,
  input [7:0] W0_addr,
  input W0_en,
  input [23:0] W0_data,
  input [3:0] W0_mask
);


  reg reg_R0_ren;
  reg [7:0] reg_R0_addr;
  reg [23:0] ram [255:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 256; initvar = initvar+1)
        ram[initvar] = {1 {$random}};
      reg_R0_addr = {1 {$random}};
    end
  `endif
  always @(posedge R0_clk)
    reg_R0_ren <= R0_en;
  always @(posedge R0_clk)
    if (R0_en) reg_R0_addr <= R0_addr;
  always @(posedge W0_clk)
    if (W0_en) begin
      if (W0_mask[0]) ram[W0_addr][5:0] <= W0_data[5:0];
      if (W0_mask[1]) ram[W0_addr][11:6] <= W0_data[11:6];
      if (W0_mask[2]) ram[W0_addr][17:12] <= W0_data[17:12];
      if (W0_mask[3]) ram[W0_addr][23:18] <= W0_data[23:18];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [31:0] R0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      R0_random = {$random};
      reg_R0_ren = R0_random[0];
    end
  `endif
  always @(posedge R0_clk) R0_random <= {$random};
  assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[23:0];
  `else
  assign R0_data = ram[reg_R0_addr];
  `endif

endmodule// name:array_4_ext depth:2048 width:4 masked:true maskGran:2 maskSeg:2
module array_4_ext(
  input R0_clk,
  input [10:0] R0_addr,
  input R0_en,
  output [3:0] R0_data,
  input W0_clk,
  input [10:0] W0_addr,
  input W0_en,
  input [3:0] W0_data,
  input [1:0] W0_mask
);


  reg reg_R0_ren;
  reg [10:0] reg_R0_addr;
  reg [3:0] ram [2047:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 2048; initvar = initvar+1)
        ram[initvar] = {1 {$random}};
      reg_R0_addr = {1 {$random}};
    end
  `endif
  always @(posedge R0_clk)
    reg_R0_ren <= R0_en;
  always @(posedge R0_clk)
    if (R0_en) reg_R0_addr <= R0_addr;
  always @(posedge W0_clk)
    if (W0_en) begin
      if (W0_mask[0]) ram[W0_addr][1:0] <= W0_data[1:0];
      if (W0_mask[1]) ram[W0_addr][3:2] <= W0_data[3:2];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [31:0] R0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      R0_random = {$random};
      reg_R0_ren = R0_random[0];
    end
  `endif
  always @(posedge R0_clk) R0_random <= {$random};
  assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[3:0];
  `else
  assign R0_data = ram[reg_R0_addr];
  `endif

endmodule// name:array_3_ext depth:256 width:24 masked:true maskGran:12 maskSeg:2
module array_3_ext(
  input RW0_clk,
  input [7:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [1:0] RW0_wmask,
  input [23:0] RW0_wdata,
  output [23:0] RW0_rdata
);


  reg reg_RW0_ren;
  reg [7:0] reg_RW0_addr;
  reg [23:0] ram [255:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 256; initvar = initvar+1)
        ram[initvar] = {1 {$random}};
      reg_RW0_addr = {1 {$random}};
    end
  `endif
  always @(posedge RW0_clk)
    reg_RW0_ren <= RW0_en && !RW0_wmode;
  always @(posedge RW0_clk)
    if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
  always @(posedge RW0_clk)
    if (RW0_en && RW0_wmode) begin
      if (RW0_wmask[0]) ram[RW0_addr][11:0] <= RW0_wdata[11:0];
      if (RW0_wmask[1]) ram[RW0_addr][23:12] <= RW0_wdata[23:12];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [31:0] RW0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      RW0_random = {$random};
      reg_RW0_ren = RW0_random[0];
    end
  `endif
  always @(posedge RW0_clk) RW0_random <= {$random};
  assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[23:0];
  `else
  assign RW0_rdata = ram[reg_RW0_addr];
  `endif

endmodule// name:array_2_ext depth:256 width:16 masked:true maskGran:1 maskSeg:16
module array_2_ext(
  input RW0_clk,
  input [7:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [15:0] RW0_wmask,
  input [15:0] RW0_wdata,
  output [15:0] RW0_rdata
);


  reg reg_RW0_ren;
  reg [7:0] reg_RW0_addr;
  reg [15:0] ram [255:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 256; initvar = initvar+1)
        ram[initvar] = {1 {$random}};
      reg_RW0_addr = {1 {$random}};
    end
  `endif
  always @(posedge RW0_clk)
    reg_RW0_ren <= RW0_en && !RW0_wmode;
  always @(posedge RW0_clk)
    if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
  always @(posedge RW0_clk)
    if (RW0_en && RW0_wmode) begin
      if (RW0_wmask[0]) ram[RW0_addr][0:0] <= RW0_wdata[0:0];
      if (RW0_wmask[1]) ram[RW0_addr][1:1] <= RW0_wdata[1:1];
      if (RW0_wmask[2]) ram[RW0_addr][2:2] <= RW0_wdata[2:2];
      if (RW0_wmask[3]) ram[RW0_addr][3:3] <= RW0_wdata[3:3];
      if (RW0_wmask[4]) ram[RW0_addr][4:4] <= RW0_wdata[4:4];
      if (RW0_wmask[5]) ram[RW0_addr][5:5] <= RW0_wdata[5:5];
      if (RW0_wmask[6]) ram[RW0_addr][6:6] <= RW0_wdata[6:6];
      if (RW0_wmask[7]) ram[RW0_addr][7:7] <= RW0_wdata[7:7];
      if (RW0_wmask[8]) ram[RW0_addr][8:8] <= RW0_wdata[8:8];
      if (RW0_wmask[9]) ram[RW0_addr][9:9] <= RW0_wdata[9:9];
      if (RW0_wmask[10]) ram[RW0_addr][10:10] <= RW0_wdata[10:10];
      if (RW0_wmask[11]) ram[RW0_addr][11:11] <= RW0_wdata[11:11];
      if (RW0_wmask[12]) ram[RW0_addr][12:12] <= RW0_wdata[12:12];
      if (RW0_wmask[13]) ram[RW0_addr][13:13] <= RW0_wdata[13:13];
      if (RW0_wmask[14]) ram[RW0_addr][14:14] <= RW0_wdata[14:14];
      if (RW0_wmask[15]) ram[RW0_addr][15:15] <= RW0_wdata[15:15];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [31:0] RW0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      RW0_random = {$random};
      reg_RW0_ren = RW0_random[0];
    end
  `endif
  always @(posedge RW0_clk) RW0_random <= {$random};
  assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[15:0];
  `else
  assign RW0_rdata = ram[reg_RW0_addr];
  `endif

endmodule// name:array_1_ext depth:512 width:308 masked:true maskGran:77 maskSeg:4
module array_1_ext(
  input RW0_clk,
  input [8:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [3:0] RW0_wmask,
  input [307:0] RW0_wdata,
  output [307:0] RW0_rdata
);


  reg reg_RW0_ren;
  reg [8:0] reg_RW0_addr;
  reg [307:0] ram [511:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 512; initvar = initvar+1)
        ram[initvar] = {10 {$random}};
      reg_RW0_addr = {1 {$random}};
    end
  `endif
  always @(posedge RW0_clk)
    reg_RW0_ren <= RW0_en && !RW0_wmode;
  always @(posedge RW0_clk)
    if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
  always @(posedge RW0_clk)
    if (RW0_en && RW0_wmode) begin
      if (RW0_wmask[0]) ram[RW0_addr][76:0] <= RW0_wdata[76:0];
      if (RW0_wmask[1]) ram[RW0_addr][153:77] <= RW0_wdata[153:77];
      if (RW0_wmask[2]) ram[RW0_addr][230:154] <= RW0_wdata[230:154];
      if (RW0_wmask[3]) ram[RW0_addr][307:231] <= RW0_wdata[307:231];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [319:0] RW0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
      reg_RW0_ren = RW0_random[0];
    end
  `endif
  always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
  assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[307:0];
  `else
  assign RW0_rdata = ram[reg_RW0_addr];
  `endif

endmodule// name:array_0_ext depth:32 width:1024 masked:true maskGran:512 maskSeg:2
module array_0_ext(
  input RW0_clk,
  input [4:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [1:0] RW0_wmask,
  input [1023:0] RW0_wdata,
  output [1023:0] RW0_rdata
);


  reg reg_RW0_ren;
  reg [4:0] reg_RW0_addr;
  reg [1023:0] ram [31:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 32; initvar = initvar+1)
        ram[initvar] = {32 {$random}};
      reg_RW0_addr = {1 {$random}};
    end
  `endif
  always @(posedge RW0_clk)
    reg_RW0_ren <= RW0_en && !RW0_wmode;
  always @(posedge RW0_clk)
    if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
  always @(posedge RW0_clk)
    if (RW0_en && RW0_wmode) begin
      if (RW0_wmask[0]) ram[RW0_addr][511:0] <= RW0_wdata[511:0];
      if (RW0_wmask[1]) ram[RW0_addr][1023:512] <= RW0_wdata[1023:512];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [1023:0] RW0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
      reg_RW0_ren = RW0_random[0];
    end
  `endif
  always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
  assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[1023:0];
  `else
  assign RW0_rdata = ram[reg_RW0_addr];
  `endif

endmodule// name:array_ext depth:32 width:108 masked:true maskGran:27 maskSeg:4
module array_ext(
  input RW0_clk,
  input [4:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [3:0] RW0_wmask,
  input [107:0] RW0_wdata,
  output [107:0] RW0_rdata
);


  reg reg_RW0_ren;
  reg [4:0] reg_RW0_addr;
  reg [107:0] ram [31:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 32; initvar = initvar+1)
        ram[initvar] = {4 {$random}};
      reg_RW0_addr = {1 {$random}};
    end
  `endif
  always @(posedge RW0_clk)
    reg_RW0_ren <= RW0_en && !RW0_wmode;
  always @(posedge RW0_clk)
    if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
  always @(posedge RW0_clk)
    if (RW0_en && RW0_wmode) begin
      if (RW0_wmask[0]) ram[RW0_addr][26:0] <= RW0_wdata[26:0];
      if (RW0_wmask[1]) ram[RW0_addr][53:27] <= RW0_wdata[53:27];
      if (RW0_wmask[2]) ram[RW0_addr][80:54] <= RW0_wdata[80:54];
      if (RW0_wmask[3]) ram[RW0_addr][107:81] <= RW0_wdata[107:81];
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [127:0] RW0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      RW0_random = {$random, $random, $random, $random};
      reg_RW0_ren = RW0_random[0];
    end
  `endif
  always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random};
  assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[107:0];
  `else
  assign RW0_rdata = ram[reg_RW0_addr];
  `endif

endmodule
module DifftestIntWriteback(
  input         io_clock,
input  [ 7:0] io_coreid,
input         io_valid,
input  [31:0] io_dest,
input  [63:0] io_data
);
`ifndef SYNTHESIS

import "DPI-C" function void v_difftest_IntWriteback (
input     byte io_coreid,
input      bit io_valid,
input      int io_dest,
input  longint io_data
);

  always @(posedge io_clock) begin
    v_difftest_IntWriteback (io_coreid,io_valid,io_dest,io_data);
  end
`endif
endmodule

module DifftestFpWriteback(
  input         io_clock,
input  [ 7:0] io_coreid,
input         io_valid,
input  [31:0] io_dest,
input  [63:0] io_data
);
`ifndef SYNTHESIS

import "DPI-C" function void v_difftest_FpWriteback (
input     byte io_coreid,
input      bit io_valid,
input      int io_dest,
input  longint io_data
);

  always @(posedge io_clock) begin
    v_difftest_FpWriteback (io_coreid,io_valid,io_dest,io_data);
  end
`endif
endmodule

module DifftestArchIntRegState(
  input         io_clock,
input  [ 7:0] io_coreid,
input  [63:0] io_gpr_0,
input  [63:0] io_gpr_1,
input  [63:0] io_gpr_2,
input  [63:0] io_gpr_3,
input  [63:0] io_gpr_4,
input  [63:0] io_gpr_5,
input  [63:0] io_gpr_6,
input  [63:0] io_gpr_7,
input  [63:0] io_gpr_8,
input  [63:0] io_gpr_9,
input  [63:0] io_gpr_10,
input  [63:0] io_gpr_11,
input  [63:0] io_gpr_12,
input  [63:0] io_gpr_13,
input  [63:0] io_gpr_14,
input  [63:0] io_gpr_15,
input  [63:0] io_gpr_16,
input  [63:0] io_gpr_17,
input  [63:0] io_gpr_18,
input  [63:0] io_gpr_19,
input  [63:0] io_gpr_20,
input  [63:0] io_gpr_21,
input  [63:0] io_gpr_22,
input  [63:0] io_gpr_23,
input  [63:0] io_gpr_24,
input  [63:0] io_gpr_25,
input  [63:0] io_gpr_26,
input  [63:0] io_gpr_27,
input  [63:0] io_gpr_28,
input  [63:0] io_gpr_29,
input  [63:0] io_gpr_30,
input  [63:0] io_gpr_31
);
`ifndef SYNTHESIS

import "DPI-C" function void v_difftest_ArchIntRegState (
input     byte io_coreid,
input  longint io_gpr_0,
input  longint io_gpr_1,
input  longint io_gpr_2,
input  longint io_gpr_3,
input  longint io_gpr_4,
input  longint io_gpr_5,
input  longint io_gpr_6,
input  longint io_gpr_7,
input  longint io_gpr_8,
input  longint io_gpr_9,
input  longint io_gpr_10,
input  longint io_gpr_11,
input  longint io_gpr_12,
input  longint io_gpr_13,
input  longint io_gpr_14,
input  longint io_gpr_15,
input  longint io_gpr_16,
input  longint io_gpr_17,
input  longint io_gpr_18,
input  longint io_gpr_19,
input  longint io_gpr_20,
input  longint io_gpr_21,
input  longint io_gpr_22,
input  longint io_gpr_23,
input  longint io_gpr_24,
input  longint io_gpr_25,
input  longint io_gpr_26,
input  longint io_gpr_27,
input  longint io_gpr_28,
input  longint io_gpr_29,
input  longint io_gpr_30,
input  longint io_gpr_31
);

  always @(posedge io_clock) begin
    v_difftest_ArchIntRegState (io_coreid,io_gpr_0,io_gpr_1,io_gpr_2,io_gpr_3,io_gpr_4,io_gpr_5,io_gpr_6,io_gpr_7,io_gpr_8,io_gpr_9,io_gpr_10,io_gpr_11,io_gpr_12,io_gpr_13,io_gpr_14,io_gpr_15,io_gpr_16,io_gpr_17,io_gpr_18,io_gpr_19,io_gpr_20,io_gpr_21,io_gpr_22,io_gpr_23,io_gpr_24,io_gpr_25,io_gpr_26,io_gpr_27,io_gpr_28,io_gpr_29,io_gpr_30,io_gpr_31);
  end
`endif
endmodule

module DifftestArchEvent(
  input         io_clock,
input  [ 7:0] io_coreid,
input  [31:0] io_intrNO,
input  [31:0] io_cause,
input  [63:0] io_exceptionPC,
input  [31:0] io_exceptionInst
);
`ifndef SYNTHESIS

import "DPI-C" function void v_difftest_ArchEvent (
input     byte io_coreid,
input      int io_intrNO,
input      int io_cause,
input  longint io_exceptionPC,
input      int io_exceptionInst
);

  always @(posedge io_clock) begin
    v_difftest_ArchEvent (io_coreid,io_intrNO,io_cause,io_exceptionPC,io_exceptionInst);
  end
`endif
endmodule

module DifftestCSRState(
  input         io_clock,
input  [ 7:0] io_coreid,
input  [ 1:0] io_priviledgeMode,
input  [63:0] io_mstatus,
input  [63:0] io_sstatus,
input  [63:0] io_mepc,
input  [63:0] io_sepc,
input  [63:0] io_mtval,
input  [63:0] io_stval,
input  [63:0] io_mtvec,
input  [63:0] io_stvec,
input  [63:0] io_mcause,
input  [63:0] io_scause,
input  [63:0] io_satp,
input  [63:0] io_mip,
input  [63:0] io_mie,
input  [63:0] io_mscratch,
input  [63:0] io_sscratch,
input  [63:0] io_mideleg,
input  [63:0] io_medeleg
);
`ifndef SYNTHESIS

import "DPI-C" function void v_difftest_CSRState (
input     byte io_coreid,
input     byte io_priviledgeMode,
input  longint io_mstatus,
input  longint io_sstatus,
input  longint io_mepc,
input  longint io_sepc,
input  longint io_mtval,
input  longint io_stval,
input  longint io_mtvec,
input  longint io_stvec,
input  longint io_mcause,
input  longint io_scause,
input  longint io_satp,
input  longint io_mip,
input  longint io_mie,
input  longint io_mscratch,
input  longint io_sscratch,
input  longint io_mideleg,
input  longint io_medeleg
);

  always @(posedge io_clock) begin
    v_difftest_CSRState (io_coreid,io_priviledgeMode,io_mstatus,io_sstatus,io_mepc,io_sepc,io_mtval,io_stval,io_mtvec,io_stvec,io_mcause,io_scause,io_satp,io_mip,io_mie,io_mscratch,io_sscratch,io_mideleg,io_medeleg);
  end
`endif
endmodule

module DifftestDebugMode(
  input         io_clock,
input  [ 7:0] io_coreid,
input         io_debugMode,
input  [63:0] io_dcsr,
input  [63:0] io_dpc,
input  [63:0] io_dscratch0,
input  [63:0] io_dscratch1
);
`ifndef SYNTHESIS

import "DPI-C" function void v_difftest_DebugMode (
input     byte io_coreid,
input      bit io_debugMode,
input  longint io_dcsr,
input  longint io_dpc,
input  longint io_dscratch0,
input  longint io_dscratch1
);

  always @(posedge io_clock) begin
    v_difftest_DebugMode (io_coreid,io_debugMode,io_dcsr,io_dpc,io_dscratch0,io_dscratch1);
  end
`endif
endmodule

module DifftestArchFpRegState(
  input         io_clock,
input  [ 7:0] io_coreid,
input  [63:0] io_fpr_0,
input  [63:0] io_fpr_1,
input  [63:0] io_fpr_2,
input  [63:0] io_fpr_3,
input  [63:0] io_fpr_4,
input  [63:0] io_fpr_5,
input  [63:0] io_fpr_6,
input  [63:0] io_fpr_7,
input  [63:0] io_fpr_8,
input  [63:0] io_fpr_9,
input  [63:0] io_fpr_10,
input  [63:0] io_fpr_11,
input  [63:0] io_fpr_12,
input  [63:0] io_fpr_13,
input  [63:0] io_fpr_14,
input  [63:0] io_fpr_15,
input  [63:0] io_fpr_16,
input  [63:0] io_fpr_17,
input  [63:0] io_fpr_18,
input  [63:0] io_fpr_19,
input  [63:0] io_fpr_20,
input  [63:0] io_fpr_21,
input  [63:0] io_fpr_22,
input  [63:0] io_fpr_23,
input  [63:0] io_fpr_24,
input  [63:0] io_fpr_25,
input  [63:0] io_fpr_26,
input  [63:0] io_fpr_27,
input  [63:0] io_fpr_28,
input  [63:0] io_fpr_29,
input  [63:0] io_fpr_30,
input  [63:0] io_fpr_31
);
`ifndef SYNTHESIS

import "DPI-C" function void v_difftest_ArchFpRegState (
input     byte io_coreid,
input  longint io_fpr_0,
input  longint io_fpr_1,
input  longint io_fpr_2,
input  longint io_fpr_3,
input  longint io_fpr_4,
input  longint io_fpr_5,
input  longint io_fpr_6,
input  longint io_fpr_7,
input  longint io_fpr_8,
input  longint io_fpr_9,
input  longint io_fpr_10,
input  longint io_fpr_11,
input  longint io_fpr_12,
input  longint io_fpr_13,
input  longint io_fpr_14,
input  longint io_fpr_15,
input  longint io_fpr_16,
input  longint io_fpr_17,
input  longint io_fpr_18,
input  longint io_fpr_19,
input  longint io_fpr_20,
input  longint io_fpr_21,
input  longint io_fpr_22,
input  longint io_fpr_23,
input  longint io_fpr_24,
input  longint io_fpr_25,
input  longint io_fpr_26,
input  longint io_fpr_27,
input  longint io_fpr_28,
input  longint io_fpr_29,
input  longint io_fpr_30,
input  longint io_fpr_31
);

  always @(posedge io_clock) begin
    v_difftest_ArchFpRegState (io_coreid,io_fpr_0,io_fpr_1,io_fpr_2,io_fpr_3,io_fpr_4,io_fpr_5,io_fpr_6,io_fpr_7,io_fpr_8,io_fpr_9,io_fpr_10,io_fpr_11,io_fpr_12,io_fpr_13,io_fpr_14,io_fpr_15,io_fpr_16,io_fpr_17,io_fpr_18,io_fpr_19,io_fpr_20,io_fpr_21,io_fpr_22,io_fpr_23,io_fpr_24,io_fpr_25,io_fpr_26,io_fpr_27,io_fpr_28,io_fpr_29,io_fpr_30,io_fpr_31);
  end
`endif
endmodule

module DifftestLrScEvent(
  input         io_clock,
input  [ 7:0] io_coreid,
input         io_valid,
input         io_success
);
`ifndef SYNTHESIS

import "DPI-C" function void v_difftest_LrScEvent (
input     byte io_coreid,
input      bit io_valid,
input      bit io_success
);

  always @(posedge io_clock) begin
    v_difftest_LrScEvent (io_coreid,io_valid,io_success);
  end
`endif
endmodule

module DifftestBasicInstrCommit(
  input         io_clock,
input  [ 7:0] io_coreid,
input  [ 7:0] io_index,
input         io_valid,
input  [ 7:0] io_special,
input         io_skip,
input         io_isRVC,
input         io_rfwen,
input         io_fpwen,
input  [31:0] io_wpdest,
input  [ 7:0] io_wdest
);
`ifndef SYNTHESIS

import "DPI-C" function void v_difftest_BasicInstrCommit (
input     byte io_coreid,
input     byte io_index,
input      bit io_valid,
input     byte io_special,
input      bit io_skip,
input      bit io_isRVC,
input      bit io_rfwen,
input      bit io_fpwen,
input      int io_wpdest,
input     byte io_wdest
);

  always @(posedge io_clock) begin
    v_difftest_BasicInstrCommit (io_coreid,io_index,io_valid,io_special,io_skip,io_isRVC,io_rfwen,io_fpwen,io_wpdest,io_wdest);
  end
`endif
endmodule

module DifftestBasicTrapEvent(
  input         io_clock,
input  [ 7:0] io_coreid,
input         io_valid,
input  [63:0] io_cycleCnt,
input  [63:0] io_instrCnt,
input         io_hasWFI
);
`ifndef SYNTHESIS

import "DPI-C" function void v_difftest_BasicTrapEvent (
input     byte io_coreid,
input      bit io_valid,
input  longint io_cycleCnt,
input  longint io_instrCnt,
input      bit io_hasWFI
);

  always @(posedge io_clock) begin
    v_difftest_BasicTrapEvent (io_coreid,io_valid,io_cycleCnt,io_instrCnt,io_hasWFI);
  end
`endif
endmodule
